1. Field of the Invention
This invention relates to a semiconductor device equipped with a field effect transistor and a method for manufacturing the same.
2. Description of the Related Art
In a MOSFET (Metal-Oxide-Semiconductor-Field Effect Transistor) belonging to a generation of 0.1 μm (gate length), it is estimated that signal delay due to parasitic resistance residing between a wiring portion and a channel region of the MOSFET, i.e. in first diffused layers formed to sandwich the channel region and second diffused layers more deeply formed to sandwich the first diffused layers will be serious.
The parasitic resistance mainly includes contact resistance, silicide resistance and extension resistance. Of these resistances, the extension resistance is attributable to the first diffused layer.
The first supposed method for reducing the extension resistance is to extend a resistance sectional area downward, i.e. to increase the thickness of the first diffused layer. The second supposed method is to shorten the resistance length, or shorten the length of the first diffused layer in a gate length direction. In the first and second methods, however, a diffused layer forming a source and another diffused layer forming a drain become near to each other so that a problem of the short channel effect of MOSFET becomes evident.
A third supposed method is to increase the impurity concentration of the first diffused layer extremely. However, the impurity concentration of impurities soluble in silicon has an upper limit. For this reason, it is difficult to improve the impurity concentration extremely from the present impurity concentration. Accordingly, there is little hope in the reduction in the extension resistance by this technique.
Thus, it was difficult to reduce the extension resistance effectively without making manifest the other problem such as the short-channel effect.
In view of this, as a fourth method, it was proposed to provide a conductive layer (hereinafter referred to as “low resistance layer”) formed between the upper surface of a first diffused layer and the lower surface of a gate side wall so as to sandwich a gate insulating film (see JP11-297991(kokai)). This method was considered to realize to reduce the extension resistance without making manifest the problem of the short channel effect.
However, the above fourth method presented a problem in consistency with an existing or present manufacturing method.
In the present manufacturing method, after the step of forming the low resistance layer, the step of high-temperature heat treatment is carried out. For example, as the step of forming the second diffused layer, the high temperature heat treatment at about 1000° C. is carried out.
On the other hand, in the fourth method, silicide of refractory metal such as Ti, Co, Pt, etc. is adopted for the low resistance layer. This low resistance layer, however, cannot have heat resistance. This made it difficult to manufacture semiconductor devices. The reason therefor is as follows. Since the silicide of the refractory metal has a melting point of about 2200° C. (about 2470 K) or lower, at an absolute temperature about 0.5 times or more as high as this melting point, i.e. at the temperature of about 960° C. (about 1230 K) or higher, atom diffusion in the silicide of the metal becomes active, thereby generating agglomeration or decomposition of the low resistance layer.
Further, generally, the silicide of the refractory metal, after metal has been deposited on the surface of the silicon substrate, is formed so that the metal consumes the silicon by heat treatment. However, it is difficult to control the consumption of the silicon by the metal so that the low resistance layer is likely to be formed to penetrate the first diffused layer. This will break a pn junction, thereby giving rise to a problem of the short-circuiting of MOSFET. This problem, in the present technique, is particularly manifest in the MOSFET from the generation of 0.1 μm (gate length) onward.